The present invention relates to a data processor which includes general purpose registers as one of the fundamental elements thereof.
Recently, there have been high demands for an increase of the storage area accessible by a program, that is, by address extension, and an increase of the data length which can be handled by an arithmetic unit, that is, by data extension. A new machine which can satisfy these demands also must satisfy the condition that the new machine can run a lot of already existing old programs which are not adapted to the new extended address range or the new enlarged data length.
One prior art system which has accomplished address extension is explained in "IBM System/370 Extended Architecture Principles of Operations" (SA-22-7085-0) published by Internatinal Business Machines Corp. According to this prior method, an address extension bit field is provided within a program status word (PSW) which controls execution of a program. If the address extension bit is "0", the address maximum value is treated as 2.sup.24 -1, while the address maximu value is treated as 2.sup.31 -1, when the address extension bit is 1. Thus, the address limit is enhanced from 24 bits to 31 bits in this way. A more detailed explantion of this technique will be given hereinafter.
According to FIG. 1, the fields R.sub.1, R.sub.2, R.sub.3, B.sub.1, B.sub.2 and X.sub.2 each represent a register number field of four bits which designates one of sixteen general purpose registers. The usage of the content of a designated general purpose register is determined according to each instruction format. For example, the fields B.sub.1 and B.sub.2 each designate a base register. The contents of the general purpose registers designated by B.sub.1 and B.sub.2, respectively, are added to the contents of displacement fields D.sub.1 and D.sub.2, to generate memory access addresses. The field X.sub.2 designates an index register. The content of a general purpose register designated by the index field X.sub.2 is added to the sum of the content of the base register B.sub.2 and the displacement D.sub.2, to generate a memory access address. The contents of registers designated by the R.sub.1 to R.sub.3 fields are used as address data on operand data, depending upon each instruction.
The length of the general purpose registers is 32 bits. According to the prior art mentioned above, the most significant one or eight bits of the content of a general purpose register designated by an instruction may be neglected, depending upon whether the address extension bit is 0 or 1. The storing of the address data into the general purpose registers is performed by a load instruction which loads 32 bits of data into a general purpose register or by an Add instruction which performs an addition of 32 bit data in the main storage and 32 bit data in a general purpose register to store the sum of 32 bits into a general purpose register. Therefore, according to this prior art system, loading of address data is performed by an instruction which deals with 32 bit data, but reading out of address data from a general purpose register is performed in such a manner as to neglect the most significant one or eight bits of the readout data, so as to generate 31 bit address data or 24 bit address data, depending upon the value of the address extension bit in the PSW.
According to our recent research, however, the need for a larger storage area accessible with addresses larger than 31 bits may be desirable in the near future; however, according to the prior art, such large addresses cannot be utilized, because of the limited bit length of the general purpose registers. One approach we considered is to extend the length of the general purpose registers to a larger value, e.g., to 64 bits. However, the conventional arithmetic operation unit in the prior art system is capable of processing the standard data length, e.g., 32 bits, and so, it is impossible to enable the arithmetic operation unit to generate 64 bits of address data in response to conventional instructions. In other words, new types of instructions are required in order to generate 64 bit address data using the conventional 32 bit arithmetic operation unit. In order to avoid usage of such new instructions, it is desirable to have an arithmetic operation unit which can handle a 64 bit arithmetic operation. Furthermore, if it is desirable to handle the conventional programs which expect to use a 32 bit arithmetic operation unit, a data processor should have both 64 bit and 32 bit arithmetic operation units. This makes it possible to selectively use the 64 bit arithmetic operation unit for newly developed programs by setting the address extension bit in the PSW to 1, and to use the 32 bit arithmetic operation unit for the conventional program by setting the address extension bit in the PSW to 0. The problem with this proposed modification of the prior art is that it is difficult to execute a program which wants to make use of the extended addresses as well as the 32 bit arithmetic operation unit.
The future need for a greater data length than the conventional 32 bits is also inevitable. However, even if we adopt 64 bit general purpose registers in the data processing system, we must make sure that the 32 bit arithmetic operation is also possible for a conventional program.
As is clear from the foregoing explanation, it is desirable for a data processor to be able to perform any of the arithmetic operations of the extended bit length (e.g., 64 bit) and the conventional bit length (e.g., 32 bit), as well as to use addresses of extended address length (e.g., 64 bits) and conventional address length (e.g., 32 bits).